The present invention relates to a decoder circuit for decoding and converting n-bit binary inputs representing a binary code into 2n thermometer outputs representing a thermometer code, and a method of designing the decoder circuit.
In order to keep the linearity of an analog output from a current type digital-to-analog converter (DAC), a decoder circuit converts n-bit binary inputs, e.g., 8-bit binary inputs representing a binary code into 2n-bit thermometer outputs, e.g., 256-bit thermometer outputs representing a thermometer code, and controls the operation of the DAC using the 2n thermometer outputs.
For instance, a truth table of a 4-bit decoder circuit for decoding and converting 4-bit binary inputs BIN<3:0> into 16-bit thermometer outputs THM<15:0> is represented by Table 1.
TABLE 1Binary input BINThermometer output THM<3><2><1><0><15><14><13><12><11><10><9><8><7><6><5><4><3><2><1><0>00000000000000000000000100000000000000010010000000000000001100110000000000000111010000000000000011110101000000000001111101100000000000111111011100000000011111111000000000001111111110010000000111111111101000000011111111111011000001111111111111000000111111111111110100011111111111111110001111111111111111110111111111111111
The following methods (1) and (2) are known to realize a 4-bit decoder circuit:
Method (1): A method involving constructing a logic circuit in accordance with the truth table represented by Table 1.
Method (2): A method involving taking AND of all the states of the 4-bit binary inputs BIN<3:0> shown in Table 1 with the use of 16 AND circuits, and setting all the thermometer outputs THM on the lower side from one AND circuit corresponding to the states of actually-input binary inputs BIN<3:0> to ‘1’.
First, Method (1) generates, for example, those algebraic expressions shown below that satisfy the truth table of Table 1, thereby realizing a specific 4-bit decoder circuit in accordance therewith.T0=B3+B2+B1+B0T1=B3+B2+B1T2=B3+B2+B1*B0T3=B3+B2T4=B3+B2*(B1+B0)T5=B3+B2*B1T6=B3+B2*B1*B0T7=B3T8=B3*(B2+B1+B0)T9=B3*(B2+B1)T10=B3*(B2+B1*B0)T11=B3*B2T12=B3*B2*(B1+B0)T13=B3*B2*B1T14=B3*B2*B1*B0T15=0
In the above, B3 to B0 represent the binary inputs BIN<3:0>, and T15 to T0 represent the thermometer outputs THM<15:0>. Note that T15, i.e., the thermometer output THM<15> is always ‘0’ regardless of the state of the binary inputs BIN<3:0>, as shown in the truth table of Table 1.
FIG. 10 is a circuit diagram showing an example of the configuration of a decoder circuit generated by Method (1). While the decoder circuit generated by Method (1) operates at high speed, the design and the configuration thereof are complicated. When a decoder circuit is of 4-bit like the decoder circuit of FIG. 10, the configuration is not very complicated; however, when a decoder circuit is of 8-bit or the like, the configuration is to be extremely complicated. In addition, it is easily imaginable that the size of the decoder circuit generated by Method (1) increases in proportion not to 2n but to n×2n, with n being the number of bits of binary inputs BIN.
FIG. 11 is a circuit diagram showing one example of the configuration of a decoder circuit generated by Method (2). The decoder circuit shown in FIG. 11 is a code converting unit 50 shown in FIG. 3 of JP 2003-46388 A including a decoder 51 that decodes an n-bit binary code value BC from a binary code generating unit 20 and outputs 2n values DC and a thermometer code converting unit 52 that converts the output values from the decoder 51 into thermometer code values TC.
In the code converting unit 50 shown in FIG. 11, first, the decoder 51 operates such that only an output from one NAND circuit ND corresponding to the state of an actually-input binary code value BC becomes ‘0’ and that one thermometer code value TC corresponding to this one NAND circuit ND becomes ‘1’. Thereafter, NOR circuits and INV circuits connected in series in the thermometer code converting unit 52 sequentially output ‘1’ as all the thermometer code values TC on the lower side from the one thermometer code value TC.
In the code converting unit 50 shown in FIG. 11, the number of inputs of each of the NAND circuits ND composing the decoder 51 varies depending on the number of bits of the binary code value BC, and in the case of 8 bits, 8-input NAND circuits are needed. Since it is not realistic to realize such an 8-input NAND circuit as it is, it is necessary to realize a circuit equivalent to an 8-input NAND circuit by, for instance, inputting outputs of two 4-input NAND circuits to a 2-input NOR circuit and an INV circuit. The circuit size of the decoder 51 increases in proportion to n×2n (or greater), with n being the number of bits of the binary code value BC.
On the other hand, the circuit size of the thermometer code converting unit 52 is only proportional to 2n and therefore, the size of the entire circuit is not so large compared to a decoder circuit generated by Method (1); however, the thermometer code converting unit 52 is not very flexible to the change in the number of bits of a binary code value BC at any rate. Furthermore, the output propagation delay time until outputting the lowest thermometer code value TC from the group of NOR circuits connected in series is to be extremely long, and this circuit is absolutely disadvantageous in terms of speeding up.
In the meantime, references related to the present invention include, in addition to JP 2003-46388 A, JP 61-165130 A, JP 62-178015 A, JP 2-26413 A, JP 7-235869 A and JP 2008-141676 A.